Pre-EVT2 & EVT2 Build ยท Goerpixel / Sony ยท Last updated: 2026-02-26
EVT2 Overall Yield
7.00%
Inline Tester (Plan B)
โฒ +3.42 pp vs Pre-EVT2
Bright Dot Loss
67.41%
1,012 pcs defective
Dark Dot Loss
10.57%
207 pcs defective
FACA Progress
0%
0 / 16 actions completed
Projected Yield (if all CA done)
8.64%
Based on CA yield gain estimates
๐ฉ Defect Category Distribution
๐ Yield Comparison โ Pre-EVT2 vs EVT2
โ FACA Status by Defect Category
๐ฏ Yield Impact by Corrective Action
๐ Defect Summary โ Quick View
Category
Defect Ratio
Qty (pcs)
Primary Root Cause
Key CA
Expected Gain
Status
โ๏ธ Yield Editor
Edit baseline yield, defect category contributions, and corrective action gains. All charts update automatically.
How to use: Edit any value below and all charts, KPIs, and the yield bridge will update automatically. Changes are saved to your browser's local storage.
๐ Baseline Yield Settings
Pre-EVT2 Baseline Yield
%
EVT2 Actual Yield (Plan B)
%
EVT2 Target Yield (POR)
%
๐ข Defect Category Ratios (% of total defects)
๐ฏ Corrective Action โ Expected Yield Gain Editor
These values represent the estimated absolute yield gain (in percentage points) from each corrective action. The Yield Bridge chart is built from these values.
Corrective Action
Category
Expected Yield Gain (pp)
Status
Realized Gain
๐๏ธ Live Yield Summary Preview
๐ Yield Bridge
Waterfall chart showing yield gain from each corrective action. Completed actions shown in solid color; pending in lighter shade.
๐ Yield Bridge โ Detailed Table
Step
Corrective Action
Category
Expected Gain (pp)
Cumulative Yield
Status
๐ฏ Yield Gap Analysis
๐ FACA Tracker
Track corrective action status per defect mode. Update status to reflect progress โ yield bridge updates automatically.
๐ Corrective Action Register
#
Category
Defect Mode
Corrective Action
Checkpoint
Expected Yield Gain
Status
Notes
๐ฌ Defect Detail โ FA Analysis
๐ก Bright Dot
๐ต Dark Dot
๐ข CP NG
๐ฃ TFE AOI NG
๐ด V-Line
Bright Dot โ Total Defect Ratio
67.41%
1,012 pcs | #1 yield detractor
BD Type Split
FE: 59.1% | BP: 40.9%
FE = Front-End OLED process | BP = Backplane IC
๐ Bright Dot โ Defect Mode Breakdown
Type
Root Cause
Ratio
Phenomenon
Type 1 (FE)
Cathode & CGL leakage
Part of 59.1%
BD in AM & PM mode; green/yellow; low contrast; dynamic
Type 2 (FE)
Cathode & CGL short by P/T on PDL footer
Part of 59.1%
BD in AM & PM mode; green/yellow; strong bright dot
Type 3 (FE)
Anode & CGL leakage (ITO particles)
Part of 59.1%
BD in AM & PM mode; blue; small portion
Type 4 (BP)
BP Ioff variation
40.9%
BD in AM mode only; green/white; higher contrast at low GL
Type 5 (BP)
TD short [Hypothesis]
Very small
BD in AM mode only; very high brightness
๐ฌ Key FA Images โ Bright Dot
These are representative FA images from the Sony/Goerpixel EVT2 failure analysis report (2026-02-26). Images show cross-sections, EDS maps, and optical micrographs of BD defect sites.
Slide 7: BD Type 1 โ CGL/Cathode Shunt SEM Cross-Section & ETL Mitigation
Slide 8: BD Type 2 โ Ti/OLED Particle Detected in Bright Dot Pixel (SEM)
Slide 9: BD Type 3 โ ITO Particle SEM Cross-Section & EDS Maps (O, In)
Slide 10: BD Type 4 โ BP Backplane Ioff Related Bright Dot
Slide 11: BD Type 5 โ High Brightness BD: Driver MOS & TD Short SEM
๐ธ FA Images
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EFA/PFA for CP NG leakage and short modes is scheduled for completion by 2026-03-05. Results will determine root cause and corrective action plan.
TFE AOI NG โ Total Defect Ratio
4.50%
263 pcs | #4 yield detractor
๐ TFE AOI NG โ Analysis
TFE AOI NG is primarily FE-related particle out of spec. Some overkill was observed at early stage. Three corrective actions are in parallel: EL mask update, particle reduction, and AOI algorithm optimization.
CA Item
Description
Checkpoint
Expected Outcome
โ EL Mask Update
EVT2 B+3 POR2 build with updated EL mask design
EVT2 (B+3) POR2 build
Reduce particle exposure area
โก Particle Reduction
Random particle reduction via EV/EN high operation rate
Ongoing monitoring
Lower particle count at TFE AOI
โข AOI Algorithm
AOI algorithm optimization for CT/AMT correlation
Overkill rate vs. CT/AMT check
Reduce overkill; stable yield
V-Line Display โ Total Defect Ratio
3.22%
56 pcs | #5 yield detractor
๐ V-Line โ Mode Breakdown
Mode
Analyzed
Ratio
Root Cause
BP CT Crosstalk
9/56
16.1%
CT: multi/single bright & dark line; crosstalk
Bonding Resistance
47/56
83.9%
Over-pressed ACF particles; module bonding related
Slide 32: V-Line Root Cause Analysis โ Bonding Process Investigation
Slide 34: LDO FPC Split-Screen FA โ ELVDD/VGH1 Micro-Short Circuit
๐ธ FA Images
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๐ก AI-Suggested Solutions โ Beyond Current Plan
Based on external research into OLED manufacturing literature, patents, and industry best practices. These are solutions that Goerpixel/Sony may not have included in the current corrective action plan.
Disclaimer: These suggestions are based on published academic research, industry patents, and manufacturing best practices. They require engineering evaluation before implementation. Potential yield gains are estimates based on literature data.
๐งน Particle Control
๐ PDL / Cathode
โก Backplane (BP)
๐๏ธ AOI / Inspection
๐ Bonding
๐ Novel / Emerging
๐ง
Effusion Cell Redesign for Cathode Deposition (Veeco-type)
Addresses: BD Type 2 (Ti particle) ยท DD Type 2 (conductive particle) ยท Estimated gain: 15โ25% reduction in particle-related BDs
Standard MBE-derived effusion cells used in OLED cathode deposition generate particles via condensation on cooler crucible surfaces and orifice inserts. Research by Veeco Instruments demonstrates that a redesigned heater assembly with optimized crucible geometry โ eliminating the reduced-diameter orifice insert โ significantly reduces particle generation. The key mechanism is preventing material condensation at the crucible orifice, which is the primary particle source. Goerpixel's current plan addresses Ti particles from the PDL process but does not appear to address particle generation from the cathode evaporation source itself. Evaluating alternative evaporation source vendors or redesigning the crucible configuration could reduce cathode-layer particle defects by 15โ25%.
High ImpactMedium EffortNot in Current Plan
๐ก
In-Situ Real-Time Particle Monitoring in Nโ Box
Addresses: All particle-related defects (BD Type 1/2/3, DD Type 2/3/4) ยท Estimated gain: Early detection prevents 5โ10% of particle-related yield loss
The current plan relies on post-process particle counting (e.g., Ti particle count post-PDL). However, real-time particle monitoring inside the Nโ enclosure during OLED deposition is not standard practice at most fabs. Installing in-situ particle counters at key deposition chambers enables immediate feedback โ if particle counts exceed threshold during a run, the panel can be flagged before committing to downstream processes. This is analogous to semiconductor fabs where in-situ monitoring is standard. The high isolation requirements of the Nโ box present challenges (traditional cleanroom monitors cannot be used), but specialized OLED Nโ box monitoring solutions are commercially available (e.g., PMeasuring OLED Nโ Box Monitoring).
High ImpactLow EffortNot in Current Plan
๐
Backside Film Contamination Inspection Before CF/OC Coating
Addresses: DD Type 4 (in-film particle in CF/OC/MLA) ยท Estimated gain: 10โ15% reduction in in-film particle DDs
EU OLED contamination research (CORDIS project) identified that film backside contamination โ not visible to standard front-side AOI โ is a major source of in-film particles that later manifest as dark dots in CF, OC, and MLA layers. The current plan does not include backside inspection before CF/OC coating. Adding a backside particle inspection step (using dark-field illumination or laser scattering) before each coating step would catch contamination events before they are buried under subsequent layers, where they become impossible to remove without destroying the panel.
Addresses: All particle defects ยท Estimated gain: Identifies contamination events that cause yield excursions
Particles generated during vacuum chamber venting and pumping cycles are a known but often unmonitored contamination source in OLED manufacturing. During vacuum breaks for maintenance or material loading, particles can be introduced into the chamber and deposit on subsequent panels. Installing residual gas analyzers (RGA) combined with particle counters at vacuum break points enables identification of contamination events before panels are processed. This is a preventive measure that can explain yield excursions that are otherwise attributed to process variation.
Medium ImpactLow EffortNot in Current Plan
๐
Undercut PDL (Negative-Taper) Geometry
Addresses: BD Type 2 (cathode-anode short via PDL footer) ยท Estimated gain: 20โ30% reduction in PDL-related BD shorts
A negative-taper (undercut) PDL profile creates a natural shadow mask effect that prevents cathode metal from continuously bridging the anode edge. This is a well-established technique used in Samsung and LG OLED fabs (documented in multiple patents and the 2025 SSRN review on OLED organic materials). The undercut geometry ensures that the cathode deposited by thermal evaporation cannot form a continuous conductive path from the pixel interior to the PDL footer, eliminating the Type 2 BD mechanism. The current Goerpixel plan uses a cathode ring redesign and SiO retention โ but does not appear to include a fundamental PDL geometry change to undercut profile, which would provide a more robust structural solution.
High ImpactMedium EffortNot in Current Plan
โฌ
Black PDL (BPDL) โ Dual Function: Isolation + Contrast
Addresses: BD Type 2 (PDL-related shorts) + display contrast improvement ยท Estimated gain: 10โ15% BD reduction + contrast ratio improvement
Replacing standard PDL with black PDL (BPDL) provides two simultaneous benefits: improved electrical isolation between cathode and anode at the pixel edge (reducing Type 2 BDs), and improved display contrast ratio by absorbing ambient light at the pixel boundary. BPDL is documented in the 2025 OLED organic materials review (SSRN) as a key advancement in AMOLED manufacturing. The black pigment in BPDL also helps mask minor particle contamination at the PDL edge that would otherwise cause visible defects. This is a process-compatible upgrade that does not require fundamental changes to the deposition sequence.
Medium ImpactMedium EffortNot in Current Plan
๐
Systematic Anode-PDL Overlap CD Monitoring
Addresses: BD Type 2/3 (anode edge exposure) ยท Estimated gain: Prevents process drift that causes yield excursions
Research published in SID Journal (2022) demonstrates that deviation of anode pattern critical dimension (CD) primarily affects the overlap of anode and PDL, directly causing cathode-anode short defects when the PDL opening extends beyond the anode edge. The current plan focuses on mask redesign but does not include systematic CD measurement of anode-PDL overlap at multiple points per panel as a process control step. Implementing SPC (Statistical Process Control) on anode-PDL overlap CD would catch process drift before it causes yield excursions, providing a preventive rather than reactive control mechanism.
Medium ImpactLow EffortNot in Current Plan
โก
LTPO Hybrid Backplane (LTPS + IGZO) for Ultra-Low Ioff
Addresses: BD Type 4 (BP Ioff variation) ยท Estimated gain: Near-elimination of BP-type BDs (Ioff reduced from nA to sub-pA range)
The current plan addresses BP Ioff variation through LDD mask re-tapeout, PMOS NW Vt implant tuning, and SAB etch profile tuning โ all of which are incremental improvements to the existing LTPS backplane. A more fundamental solution is migrating to LTPO (Low Temperature Polycrystalline Oxide) hybrid backplane, which combines LTPS for driving TFTs with IGZO (indium gallium zinc oxide) for switching TFTs. IGZO TFTs achieve Ioff in the sub-pA range (vs. nA for LTPS), which would effectively eliminate the BP Ioff variation mechanism entirely. This technology is used in Apple Watch Series 7+ and iPhone 15 Pro displays. While this is a longer-term solution requiring significant process investment, it should be evaluated as a roadmap item for EVT3 and beyond.
High ImpactHigh Effort (Long-term)Not in Current Plan
๐
Leakage Prevention Method (LPM) Pixel Circuit
Addresses: BD Type 4 (BP Ioff variation) ยท Estimated gain: 30โ50% reduction in Ioff-related BD without process changes
Published in IEEE Transactions on Electron Devices (Lin et al., 2022), the Leakage Prevention Method (LPM) uses a dedicated LPM transistor in the pixel circuit to balance off-currents at the gate node of the driving TFT, eliminating OLED current drop due to Ioff variation. This is a pixel circuit design change โ not a process change โ meaning it can be implemented without modifying the LTPS process flow. The LPM approach has been validated in AMOLED smartwatch displays and achieves significant Ioff compensation. This is a near-term solution that could be implemented in the EVT2-POR or EVT3 build without requiring a new process qualification.
High ImpactMedium EffortNot in Current Plan
๐ง
HโO High-Pressure Post-Annealing (HPPA) for LTPS TFT
Addresses: BD Type 4 (BP Ioff uniformity) ยท Estimated gain: Significant improvement in Ioff mean and sigma without mask changes
Research by Yoo et al. (2023, ScienceDirect) demonstrates that HโO high-pressure post-annealing (HPPA) significantly improves both LTPS and a-IGZO TFT uniformity and reliability. The treatment passivates interface traps and reduces threshold voltage variation, directly improving Ioff uniformity across the panel. This is a process-level fix that does not require mask changes or circuit redesign, making it a relatively low-risk addition to the existing LTPS process flow. The current Goerpixel plan does not include HPPA as a corrective action for BP Ioff variation.
Medium ImpactLow EffortNot in Current Plan
๐งช
NBTI/HCI Stress Pre-Screening of Backplane
Addresses: BD Type 4/5 (BP weak TFTs) ยท Estimated gain: Screens out weak TFTs before OLED deposition
Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) are the two primary reliability degradation mechanisms in LTPS TFTs. Pre-aging the backplane at elevated temperature and voltage before OLED deposition screens out TFTs that would fail early in the field โ converting field failures into manufacturing rejects where they can be caught and analyzed. This is standard practice in high-reliability display manufacturing but is not mentioned in the current Goerpixel corrective action plan. The current plan mentions HCI and NBTI qualification checks for the LDD re-tapeout but does not include pre-screening as a yield improvement tool.
Medium ImpactLow EffortNot in Current Plan
๐ค
AI/ML Re-classification to Reduce AOI False Positives (Overkill)
Addresses: TFE AOI NG (overkill) ยท Estimated gain: 30โ50% reduction in overkill rate based on published ML results
Research published in TechRxiv (2025) demonstrates that machine learning classifiers applied to AOI tabular data reduce false positive rates by 30โ50% without any hardware changes. The key insight is training the classifier on confirmed overkill cases from CT/AMT correlation data โ which Goerpixel already has from the EVT2 build. The current plan mentions AOI algorithm optimization for CT/AMT correlation, but this appears to be a threshold-tuning approach. A full ML re-classification system would be significantly more powerful, as it can learn complex non-linear decision boundaries that rule-based threshold systems cannot capture. The 2026 AI-powered OLED paper (Journal of Materials Chemistry C) further confirms that deep learning is now proven effective for OLED manufacturing defect detection and classification.
High ImpactMedium EffortPartially in Plan (enhanced version)
๐ก
Multi-Modal AOI: EL + Reflectance (Dark-field + Bright-field)
Addresses: TFE AOI NG (classification accuracy) ยท Estimated gain: Improved defect type classification, reduced overkill
Standard TFE AOI uses only electroluminescence (EL) imaging. Combining EL AOI with reflectance AOI (dark-field and bright-field illumination) at the same inspection station provides multi-modal information that dramatically improves defect classification accuracy. For example, a particle that causes an EL anomaly can be simultaneously imaged in reflectance to determine its size, shape, and surface properties โ enabling automated classification of BD Type 1 vs. Type 2 vs. Type 3 without manual FA. This reduces both overkill (false positives) and underkill (false negatives) simultaneously. This approach is used in advanced semiconductor AOI systems but has not been widely adopted in OLED display manufacturing.
Fixed AOI thresholds applied uniformly across the panel and across lots cause systematic overkill in regions with known higher baseline variation (e.g., panel edges vs. center). Implementing adaptive thresholds that adjust based on within-panel position and lot-to-lot baseline variation would reduce systematic overkill without increasing underkill. This is a software-only change to the AOI system that can be implemented rapidly. The position-dependent threshold approach is particularly relevant for TFE AOI where edge effects from the encapsulation process create systematic EL non-uniformity that is not a true defect.
Medium ImpactLow EffortNot in Current Plan
๐
Laser-Assisted ACF Bonding (LAB) for Uniform Heat Distribution
Laser-assisted bonding (LAB) provides more uniform heat distribution than conventional thermocompression bonding, reducing the occurrence of over-pressed ACF particles that cause V-line defects. In thermocompression bonding, the heating element contacts the bonding tool, creating temperature gradients that result in non-uniform particle compression. LAB uses a laser to heat the bonding area directly and uniformly, achieving more consistent particle deformation across the entire bonding width. This technology is used in high-end display fabs (particularly for flexible OLED bonding) and has been shown to reduce bonding-related yield loss by 40โ60%. The current plan optimizes ACF pressure and particle softness but does not consider the bonding method itself.
High ImpactMedium EffortNot in Current Plan
๐
NCA + Solder Bump Hybrid Bonding for Critical I/O Pads
For critical I/O pads where bonding resistance is most sensitive, replacing ACF with a non-conductive adhesive (NCA) combined with solder bump interconnects eliminates ACF particle over-compression entirely. In this hybrid approach, electrical connection is made through solder bumps (which are not sensitive to compression variation) while the NCA provides mechanical adhesion and environmental protection. This approach is used in high-reliability display bonding and eliminates the fundamental mechanism causing 83.9% of V-line defects. While requiring a pad design change, it provides a permanent solution rather than an optimization of the existing ACF process.
High ImpactHigh EffortNot in Current Plan
๐ก
OC Layer Dielectric Optimization to Prevent CT Crosstalk
Addresses: V-Line (BP CT crosstalk) ยท Estimated gain: May reduce 16.1% of V-line defects from crosstalk
The OC (overcoat) protection layer added in Plan B+1 should be evaluated for its dielectric constant and thickness. An excessively thick or high-permittivity OC layer can increase parasitic capacitance between adjacent signal lines, potentially exacerbating the CT crosstalk that causes 16.1% of V-line defects. The current plan does not appear to include a dielectric characterization of the OC layer in relation to crosstalk. Optimizing OC layer thickness and material selection (lower dielectric constant) could reduce parasitic capacitance and mitigate crosstalk-related V-lines without requiring BP circuit changes.
Addresses: Post-fabrication yield recovery for BD/DD rejects ยท Estimated gain: Convert 5โ15% of rejects to passing panels
Hummink's NAZCA system enables localized additive microprinting to repair individual defective pixels or interconnects post-fabrication. This is a yield recovery tool that can convert some BD/DD rejects into passing panels by depositing conductive or insulating material at the defect site to restore pixel function. For Type 2 BD defects (cathode-anode short via Ti particle), the repair involves depositing an insulating material over the particle to break the short. For open-circuit DDs (Type 4 no-abnormal FE), the repair involves depositing a conductive bridge. This technology is commercially available and has been demonstrated in OLED display repair applications. It is not a process fix but a yield recovery tool that can improve overall output without changing the manufacturing process.
High Impact (Yield Recovery)Medium EffortNot in Current Plan
๐ง
AI-Powered Defect Root Cause Classification from EL Images
Addresses: FA cycle time reduction ยท Estimated gain: Reduce FA cycle time from days to hours; enable faster CA implementation
Deep learning models trained on EL images can classify defect types (BD Type 1/2/3/4, DD Type 2/3/4) automatically, reducing FA cycle time from days to hours. The 2026 AI-powered OLED paper (Journal of Materials Chemistry C, Sarma & Chatterjee) confirms that ML and deep learning are proven effective for OLED manufacturing defect detection and classification. The current FA process requires manual microscopy, FIB/SEM, and EDS analysis for each defect โ a process that takes 2โ5 days per defect type. An automated EL-image-based classifier could triage defects in minutes, directing only ambiguous cases to manual FA. This would accelerate the corrective action feedback loop significantly, enabling faster yield improvement iterations.
High Impact (Speed)Medium EffortNot in Current Plan
โก
ESD Monitoring at Key Transfer Points
Addresses: BD/DD defects misclassified as process defects ยท Estimated gain: Identifies and eliminates ESD-induced yield loss
Electrostatic discharge (ESD) events during panel handling can create BD and DD defects that are indistinguishable from process-induced defects in standard FA. ESD damage typically manifests as pixel shorts (BD) or opens (DD) at the anode-cathode interface, with no visible particle or contamination. The current FA plan does not include ESD as a potential root cause for the "no abnormal found" DD cases (18.2% of analyzed DDs). Adding ESD monitoring at key transfer points โ post-PDL, post-OLED deposition, and post-TFE โ using wrist strap monitors, ionizers, and ESD event loggers would identify if ESD is contributing to yield loss. This is a low-cost, high-value diagnostic step.
Medium ImpactLow EffortNot in Current Plan
๐ก๏ธ
Spotless Hybrid TFE Stack with Self-Planarizing Organic Layer
Addresses: DD Type 4 (in-film particle in TFE/OC layers) ยท Estimated gain: Reduces particle-induced dark spots in encapsulation layers
Research on "spotless" hybrid TFE stacks (ScienceDirect) demonstrates that a hybrid inorganic/organic TFE architecture with an optimized self-planarizing organic interlayer significantly reduces particle-induced dark spots. The organic interlayer flows around particles during deposition, burying them and preventing them from creating pinholes in the subsequent inorganic barrier layer. The current TFE process likely uses a standard inorganic/organic stack, but the specific organic layer formulation and thickness may not be optimized for particle burial. Evaluating a thicker or lower-viscosity organic interlayer formulation could reduce DD Type 4 defects from in-film particles in the TFE stack.
Medium ImpactMedium EffortNot in Current Plan
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